1. Field of Art
The disclosure generally relates to the field of static timing analysis and more specifically to capturing the effect of waveform distortion in a static timing analysis.
2. Description of the Related Art
Integrated circuit designs are simulated to assess their performance and determine whether the design works as expected. For instance a circuit design may be simulated to determine the behavior of the circuit design in response to certain input signals. Circuit designs may also be analyzed to determine whether the different stages of the circuit meet certain timing requirements. For instance, a circuit design is analyzed to determine whether the propagation delay of a timing path is within the setup time and the hold time of a flip-flop connected to the end of the timing path.
As the density of components in integrated circuits increases and feature width becomes smaller, the cell delays become more sensitive to input waveform shapes. At high densities of integrated circuits, the waveform distortion becomes stronger due to low operating voltage, longer relative interconnect length, and stronger miller capacitance. Existing simulation techniques, for example, systems that perform composite current source timing calculations are efficient at runtime but provide less accurate results due to waveform shape distortion. Other existing techniques, for example, systems that perform full-waveform composite current source noise calculations provide high accuracy but are slow since they perform intensive circuit simulation. Accordingly, current techniques can either achieve good performance or achieve high accuracy but fail to achieve both.